1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacture, and particularly to a method for forming a metal gate.
2. Description of Prior Art
In the wake of an ever increasing integration level of semiconductor devices, a mainstream method for fabricating MOS transistor of a semiconductor device generally includes a gate dielectric layer having a high k material which has a dielectric constant of larger than or equal to ten, and a gate having metal material. In a method for forming a metal gate on a high k gate dielectric layer, an interlayer dielectric layer is typically polished by a chemical mechanical polishing (CMP) process before removing a polysilicon dummy gate. The CMP process of the interlayer dielectric layer is important for performance of the metal gate formed in subsequent steps. A conventional method for forming a metal gate is disclosed in, for example US Patent Publication No. 20100109088.
FIGS. 1-5 exemplarily show a conventional method for forming a metal gate.
As shown in FIG. 1, a transistor comprises a substrate 1 and a dummy gate 2 formed on a substrate 1. The dummy gate 2 is formed of polysilicon. Silicon oxide spacers 3 are formed on sidewalls of the dummy gate 2. A silicon nitride stop layer 4 and an interlayer dielectric layer 5 are respectively formed on the substrate 1 and cover the dummy gate 2 and the silicon oxide spacers 3. A drain/source region (not shown) may be formed on the substrate 1 and opposite sides of the dummy gate 2.
As shown in FIG. 2, the interlayer dielectric layer 5 is polished by a CMP process until the silicon nitride stop layer 4 on the dummy gate 2 is exposed.
As shown in FIG. 3, the silicon nitride stop layer 4 and the interlayer dielectric layer 5 are further polished by a CMP process until the dummy gate 2 is exposed. The silicon nitride stop layer 4 is subject to shape of the silicon oxide spacers 3, and has removal rate different from that of the silicon oxide, slurry used in the CMP process is remained on the silicon nitride stop layer 4 for a short time. Instead, most of the slurry is remained on the interlayer dielectric layer 5 close to the silicon nitride stop layer 4. Removal rate of the interlayer dielectric layer 5 close to the silicon nitride stop layer 4 is different from removal rate of the interlayer dielectric layer 5 far away from the silicon nitride stop layer 4. As a result, when the dummy gate 2 is exposed and is in flush with the silicon nitride stop layer 4, the interlayer dielectric layer 5 close to the silicon nitride stop layer 4 is lower than the dummy gate 2 and the silicon nitride stop layer 4. Recesses may be formed between adjacent dummy gates 2.
As shown in FIG. 4, the dummy gate 2 is removed to expose the substrate 1 for forming a trench (not labeled) between the silicon oxide spacers 3. A high k dielectric layer (not labeled) is formed in the trench. A metal layer 6 is deposited and filled the trench to cover the high k dielectric layer and the interlayer dielectric layer 5.
Referring to FIG. 5, the metal layer 6 is polished by a CMP process to expose the interlayer dielectric layer 5 for forming a metal gate 7. Due to recesses between adjacent dummy gates 2, metal residuals 8 may be remained on the interlayer dielectric layer 5, causing a deterioration of electrical performance.